SyntheSys Research BSA17500CSiThe SyntheSys Research BERTScope 17500CSi advanced the BERTScope Family to 17.5 Gb/s and covers today’s serial data interfaces from 1Gb Ethernet (GbE) to 10 GbE and are designed to address future serial data interfaces including:
16x Fibre Channel
12 Gb/s SAS
8.0 GT/s Gen. 3 PCI Express®
Potential 16.0 GT/s Gen. 4 PCI Express
Proprietary chip interfaces
Next Generation Backplanes
Specifications and features of the BSA17500CSI BERTScope include:
BER analysis with patented error location analysis
BER correlated eye diagram & mask testing
MJSQ1 compliant dual-Dirac based Jitter Peak analysis
Q-Factor BER-based view of vertical eye openingBER contour analysis with contour compliance masktesting for compliance masks specified at deep BER levels
Automated jitter tolerance compliance and margin testing
Jitter Map, available as an option, performs jitter decomposition using BER based measurements, including on jitter separation on long patterns such as PRBS-31.
FIR Explorer, easily converts insertion loss measurements into FIR tap settings for emulation or correction.
Rear panel diffeial reference clock outputs and single ended reference clock input at seven selectable frequencies; these may be used to phase lock a BERTScope to another BERTScope or other external instrument.
Windows XP for better web security and compatibility with local IT policies.
128Mb RAM memory enables the use and capture of extremely long stress patterns.
USB port count increased from two to four
The BERTScope 17500CSi provides rear panel diffeial reference clock outputs and single ended reference clock input which can be used to phase lock to the BSA. The rear panel reference clocks frequencies are:
10 MHz
100 MHz
106.25 MHz
133.33 MHz
156.25 MHz
166.67 MHz
200 MHz
The SyntheSys Research BERTScope 17500CSi includes:
pattern generation
error detection
eye diagram analysis and Mask Testing
Physical Layer Analysis
Error Correction
Coding and Mapping
Enhanced stress generation with added SJ range
SSC capability
Automated jitter tolerance testing
Additional options include:
Jitter Map
PatternVu Equalization Processing
PCIe stress generation
F/2 jitter generation
Live Data Analysis
SyntheSys Research BSA17500CSI - Datasheet (2 MB)